1. Field of the Invention
The present invention relates to a plasma display utilized for a flat television, an information display and the like, and a driving method thereof. Particularly, the present invention relates to a plasma display and a driving method thereof intended to protect a built-in circuit and a driving method thereof.
2. Description of the Related Art
A plasma display panel generally presents the following characteristics. A plasma display panel has a thin structure. It hardly generates flickers. It provides a high display contrast. It may be produced as a relatively large screen. It provides a high response speed. It is self-light-emitting type, and may provide multiple color light emission by means of the phosphor. Therefore, it has been widely utilized in the field of computer-related display, the field of color image display, and the like.
The plasma display is classified into an AC type in which electrodes are coated by dielectric and operated indirectly under the state of alternating-current discharge, and a DC type in which electrodes are exposed to discharge space and operated directly under the state of direct-current discharge. The AC type plasma display is classified into a memory operation type in which memory of display cell is utilized as a driving method, and a refresh operation type that does not utilize the memory. Luminance of plasma display is proportional to the number of discharge. The refresh type is mainly used for the plasma display of a small display capacity since the luminance reduces as the display capacity becomes larger.
FIG. 1 is a perspective view exemplifying a display cell configuration of the AC type plasma display.
The display cell is provided with two insulated substrates 101 and 102 made up of glass. The insulated substrate 101 is a rear substrate, and the insulated substrate 102 is a front substrate.
Transparent scanning electrodes 103 and transparent common electrodes 104 are provided on a side of the insulated substrate 102 facing the insulated substrate 101. The scanning electrodes 103 and the common electrodes 104 extend in the horizontal direction (transverse direction) of a panel. Further, trace electrodes 105 and 106 are arranged so as to superpose the scanning electrodes 103 and the common electrodes 104 respectively. The trace electrodes 105 and 106 are made of metal, for example, and provided to reduce electrode resistance between each electrode and an external drive unit. Moreover, a dielectric layer 112 that covers the scanning electrodes 103 and the common electrodes 104, and a protective layer 114 made up of magnesium oxide or the like that protects the dielectric layer 112 from discharge are provided.
Data electrodes 107, which are orthogonal to the scanning electrodes 103 and the common electrodes 104, are provided on a side of the insulated substrate 101 facing the insulated substrate 102. Accordingly, the data electrodes 107 extend in perpendicular direction (longitudinal direction) of the panel. Further, partition walls 109 that separate the display cell in the horizontal direction are provided. Further, a dielectric layer 113 covering the data electrodes 107 is provided, and phosphor layer 111, which transforms ultraviolet ray generated due to discharge of discharge gas into visible light 110, is formed on a side of each of the partition walls 109 and a surface of the dielectric layer 113. Then, the partition walls 109 secure discharge gas space 108 in the space between the insulated substrates 101 and 102, and the discharge gas such as Helium, Neon, Xenon or the like, or mixed gas composed of these gases is filled into the discharge gas space 108.
FIG. 2 is a block diagram showing a conventional AC type plasma display. N pieces (n: natural number) of the scanning electrodes 3-1 to 3-n (103) and n pieces of the common electrodes 4-1 to 4-n (104), both of which extend in row direction, are provided alternately with a predetermined space, and m pieces (m: natural number) of the data electrodes 10-1 to 10-n (107) extending in column direction so as to be orthogonal to the scanning electrodes 3-1 to 3-n (103) and the common electrodes 4-1 to 4-n (104) are provided to the PDP 1. Therefore, (n×m) pieces of display cells are provided to the PDP 1.
The conventional plasma display is provided with a power source for driving 21, a controller 22, a scanning driver 23, a scanning pulse driver 24, a sustaining driver 25, and a data driver 26, as driving circuits for the PDP 1.
The power source for driving 21 generates a logic voltage Vdd of 5V, a data voltage Vd of about 70V, and a sustaining voltage Vs of about 170V, and also generates a priming voltage Vp of about 400V, a scanning base voltage Vbw of about 100V, and a bias voltage Vsw of about 180V based on the sustaining voltage Vs. The logic voltage Vdd is supplied to the controller 22. The data voltage Vd is supplied to the data driver 26. The sustaining voltage Vs is supplied to the scanning driver 23 and the sustaining driver 25. The priming voltage Vp and the scanning base voltage Vbw are supplied to the scanning driver 23. The bias voltage Vsw is supplied to the sustaining driver 25.
The controller 22 is a circuit that generates scanning driver control signals (Sscd 1 to Sscd 6), scanning pulse driver control signals (Sspd 11 to Sspd 1n, and Sspd 21 to Sspd 2n), sustaining driver control signals (Ssud 1 to Ssud 3); and data driver control signals (Sdd 11 to Sdd 1m, and Sdd 21 to Sdd 2m), based on a video signal Sv supplied from the outside. The scanning driver control signals Sscd 1 to Sscd 6 are supplied to the scanning driver 23. The scanning pulse driver control signals Sspd 11 to Sspd 1n and Sspd 21 to Sspd 2n are supplied to the scanning pulse driver 24. The sustaining driver control signals Ssud 1 to Ssud 3 are supplied to the sustaining driver 25. The data driver control signals Sdd 11 to Sdd 1m and Sdd 21 to Sdd 2m are supplied to the data driver 26.
The scanning driver 23 is composed of six switches 23-1 to 23-6, for example, as shown in FIG. 3. The priming voltage Vp is applied to one end of the switch 23-1, and the other end of the switch 23-1 is connected to a positive line 27. The sustaining voltage Vs is applied to one end of the switch 23-2, and the other end of the switch 23-2 is connected to the positive line 27. One end of the switch 23-3 is grounded, and the other end of the switch 23-3 is connected to a negative line 28. The scanning base voltage Vbw is applied to one end of the switch 23-4, and the other end of the switch 23-4 is connected to the negative line 28. One end of the switch 23-5 is grounded, and the other end of the switch 23-5 is connected to the positive line 27. One end of the switch 23-6 is grounded, and the other end is connected to the negative line 28. The switches 23-1 to 23-6 are turned ON/OFF based on the scanning driver control signals Sscd 1 to Sscd 6, respectively, and a voltage of a predetermined waveform is supplied to the scanning pulse driver 24 via the positive line 27 and the negative line 28.
The scanning pulse driver 24 is composed of n pieces of switches 24-11 to 24-1n, n pieces of switches 24-21 to 24-2n, n pieces of diodes 24-31 to 24-3n, and n pieces of diodes 24-41 to 24-4n, for example, as shown in FIG. 3. The diodes 24-31 to 24-3n are connected in parallel to both ends of the switches 24-11 to 24-1n respectively, and the diodes 24-41 to 24-4n are connected in parallel to both ends of the switches 24-21 to 24-2n respectively. Further, the switch 24-1a (a: natural number equal to n or less) and the switch 24-2a are cascaded, each of the other ends of the switches 24-11 to 24-1n is connected to the negative line 28 in common, and each of the other ends of the switches 24-21 to 24-2n is connected to the positive line 27 in common. Moreover, the connection point between the switch 24-1a and the switch 24-2a is connected to the scanning electrode 3-a arranged on an a-th row from the top of the PDP 1. The switches 24-11 to 24-1n and 24-21 to 24-2n are turned ON/OFF based on the scanning pulse driver control signals Sspd 11 to Sspd 1n and Sspd 21 to Sspd 2n respectively, and voltages of a predetermined waveform Psc1 to Pscn are sequentially supplied to the scanning electrodes 3-1 to 3-n. 
The sustaining driver 25 is composed of three switches 25-1 to 25-3, for example, as shown in FIG. 4. The sustaining voltage Vs is applied to one end of the switch 25-1, and the common electrodes 4-1 to 4-n are connected to the other end of the switch 25-1 in common. One end of the switch 25-2 is grounded, and the common electrodes 4-1 to 4-n are connected to the other end of the switch 25-2 in common. The bias voltage Vsw is applied to one end of the switch 25-3, and the common electrodes 4-1 to 4-n are connected to the other end of the switch 25-3 in common. The switches 25-1 to 25-3 are turned ON/OFF based on the sustaining driver control signals Ssud 1 to Ssud 3 respectively, and a voltage of a predetermined waveform Psu is supplied simultaneously to the common electrodes 4-1 to 4-n. 
The data driver 26 is composed of m pieces of switches 26-11 to 26-1m, m pieces of switches 26-21 to 26-2m, m pieces of diodes 26-31 to 26-3m, and m pieces of diodes 26-41 to 26-4m, for example, as shown in FIG. 5. The diodes 26-31 to 26-3m are connected in parallel to both ends of the switches 26-11 to 26-1m respectively, and the diodes 26-41 to 26-4m are connected in parallel to both ends of the switches 26-21 to 26-2m. The switch 26-1b (b: natural number equal to m or less) and the switch 26-2b are cascaded, each of the other ends of the switches 26-11 to 26-1m is connected to the ground in common, and each of the other ends of the switches 26-21 to 26-2m is connected to the data voltage Vd in common. Moreover, the connection point between the switch 26-1b and the switch 26-2b is connected to the data electrode 10-b arranged on a b-th row from the left of the PDP 1. The switches 26-11 to 26-1m and 26-21 to 26-2m are turned ON/OFF based on the data driver control signals Sdd 11 to Sdd 1m and Sdd 21 to Sspd 2m respectively, and voltages of a predetermined waveform Pd1 to Pdm are sequentially supplied to the data electrodes 10-1 to 10-m. 
Next, a write-selective driving operation of the conventional plasma display composed in the foregoing manner will be described. FIG. 6 is a timing chart showing the write-selective driving operation of the conventional plasma display. This write-selective driving operation adopts a sub-field method, and each sub-field is provided with four periods of a priming period Tp, an addressing period Ta, a sustaining period Ts, and a charge-erasing period Te, which are sequentially set. Hereinafter, a reference potential of the scanning electrode and the common electrode is set to the sustaining voltage Vs, and a potential higher than the sustaining voltage Vs is referred to as a positive polarity and a potential lower than the sustaining voltage Vs is referred to as a negative polarity. Further, a reference potential of the data electrode is set to a ground potential GND, and a potential higher than the ground potential GND is a positive polarity and a potential lower than the ground potential GND is a negative polarity.
In the priming period Tp, the controller 22 starts generating the scanning driver control signals Sscd 1 to Sscd 6, the sustaining driver control signals Ssud 1 to Ssud 3, and the scanning pulse driver control signals Sspd 11 to Sspd in and Sspd 21 to Sspd 2n, based on the video signal Sv supplied from the outside. The controller 22 also starts generating the data driver control signals Sdd 11 to Sdd 1m having a level based on the video signal Sv and the low level data driver signals Sdd 21 to Sdd 2m. Then the controller 22 supplies the control signals to the predetermined drivers.
As a result, in the priming period Tp, the high level scanning driver control signal Sscd 1 turns the switch 23-1 ON, and the high level sustaining driver control signals Ssud 2 turns the switch 25-2 ON. Therefore, the priming pulse Pprp of positive polarity is applied to all the scanning electrodes 3-1 to 3-n, and the priming pulse Pprp of negative polarity is applied to all the common electrodes 4-1 to 4-n. Accordingly, the priming discharge occurs in the discharge gas space 108 in the vicinity of inter-electrode gap between the scanning electrodes 103 (3-1 to 3-n) and the common electrodes 104 (4-1 to 4-n), in all the display cells. Thus, active particles, which make discharge of the display cell occur easily, are generated in the discharge gas space 108, negative wall charge adheres to the scanning electrodes 3-1 to 3-n, positive wall charge adheres to the common electrodes 4-1 to 4-n, and the positive wall charge adheres to the data electrodes 10-1 to 10-m. 
Subsequently, the sustaining driver control signal Ssud 2 falls down to a lower level to turn the switch 25-2 OFF, and the sustaining driver control signal Ssud 1 rises up to a higher level to turn the switch 25-1 ON. Then, the scanning driver control signal Sscd 2 falls down to a lower level to turn the switch 23-2 OFF, and the scanning driver control signal Sscd 3 rises up to a higher level to turn the switch 23-3 ON. Therefore, a priming elimination pulse Ppre is applied to all the scanning electrodes 3-1 to 3-n after the potential of all the common electrodes 4-1 to 4-n is held at the sustaining voltage Vs of about 170V. Thus, weak discharge occurs in all the display cells. Accordingly, the negative wall charge on the scanning electrodes 3-1 to 3-n, the positive wall charge on the common electrodes 4-1 to 4-n, and the positive wall charge on the data electrodes 10-1 to 10-m reduce.
Next, in the initial state of the addressing period Ta, the high level sustaining driver control signal Ssud 3 turns the switch 25-3 ON, and the high level scanning driver control signal Sscd 4 and Sscd 5, which have been supplied from the latter priming period, turn the switches 23-4 and 23-5 ON. Accordingly, a bias pulse Pbp of positive polarity (bias voltage Vsw) is applied to all the common electrodes 4-1 to 4-n, and the potential of the pulses Psc 1 to Psc n applied to all the scanning electrodes 3-1 to 3-n is once held at the scanning base voltage Vbw.
In this state, the scanning pulse driver control signals Sspd 11 to Sspd 1n fall down sequentially to a lower level, and the scanning pulse driver control signals Sspd 21 to Sspd 2n rise up sequentially to a higher level synchronizing the signals Sspd 11 to Sspd 1n, and thus the switches 24-11 to 24-1n are sequentially turn e d OFF and the switches 24-21 to 24-2n are sequentially turned ON. Moreover, although not shown, the data drive control signals Sdd 11 to Sdd 1m rise up to a higher level based on the video signal Sv synchronously with the foregoing, and the data driver control signals Sdd 21 to Sdd 2m fall down synchronizing the signals Sdd 11 to Sdd 1m, and thus the switches 26-11 to 26-1m are turned ON based on the video signal Sv and the switches 26-21 to 26-2m are turned OFF. Thus, if writing is performed in the display cell at the a-th row and the b-th column, the scanning pulse Pwsn of negative polarity is applied to the scanning electrode 3-a, and the data pulse Pdb of positive polarity is simultaneously applied to the data electrode 10-b at the b-th column. As a result, matrix discharge occurs in the display cell at a-th row and b-th column, and furthermore, surface discharge triggered by the matrix discharge occurs between the scanning electrode and the common electrode as writing discharge and the wall charge adheres to the electrodes. On the other hand, the display cell where no writing discharge occurred is in the state where the wall charge quantity after the charge-erasing in the priming period Ta remains small.
Next, in the sustaining period Ts, the scanning driver control signals Sscd 2 and Sscd 6 alternately rise up/fall down repeatedly for the number of times corresponding to the sub-field. As a result, the switches 23-2 and 23-6 repeat ON/OFF alternately. Further, the sustaining driver control signals Ssud 1 and Ssud 2 alternately rise up/fall down repeatedly for a number of times corresponding to the sub-field synchronously with the foregoing. As a result, the switches 25-1 and 25-2 repeat ON/OFF alternately. Accordingly, sustaining pulses Psun 1 of negative polarity are applied to all the scanning electrodes 3-1 to 3-n for the number of times corresponding to the sub-field, and sustaining pulses Psun 2 of negative polarity are applied to all the common electrodes 4-1 and 4-n exclusively against the sustaining pulse Psun 1. Since the wall charge quantity of the display cell in which writing has not been performed in the addressing period Ta is extremely small, sustaining discharge does not occur even if the sustaining pulse is applied to the display cell. On the other hand, since the positive charge and the negative charge are respectively adhered to the scanning electrodes and the common electrodes in the display cell in which the writing discharge occurred in the addressing period Ta, the sustaining pulse and a wall charge voltage are superposed with each other, and the voltage between the electrodes exceeds a discharge starting voltage to occur discharge.
Next, in the charge-erasing period Te, the scanning driver control signal Sscd 3 rises up to turn the switch 23-3 ON. As a result, a charge eliminating pulse Peen of negative polarity is applied to all the scanning electrodes 3-1 to 3-n. Accordingly, weak discharge occurs in all the display cells. Thus, the wall charge accumulated on the scanning electrode and the common electrode in the display cells, which have been emitting light in the sustaining period Ts, is eliminated and the charge state of all the display cells is made uniform.
Then, the sub-field as described above is repeated to compose one field. The number of the sustaining pulse is changed in each sub-field, and gradation expression can be realized by combination of the sub-fields. Accordingly, if the ratio of the number of sustaining pulse for each sub-field is set in 1:2:4:8:16:32:64:128, for example, 256 (=28) gradations can be expressed.
In such a plasma display, power loss in the data driver greatly fluctuates depending on a video to be displayed, and power consumption of entire plasma display greatly depends on the maximum power loss in the data driver. For this reason, various displays in which power loss reduction in the data driver is intended are proposed (Japanese Patent No. 2853537, Japanese Patent Laid-Open No. Hei 11-38930). FIG. 7 is a block diagram showing a display disclosed in Japanese Patent Laid-Open No. Hei 11-38930.
In the display disclosed in Japanese Patent No. 2853537, an address current consumed in a unit of one frame, that is, a current value supplied from the data driver, is detected, and an addressing frequency is reduced when the value exceeds a predetermined value.
Further, in the display disclosed in Japanese Patent Laid-open No. Hei 11-38930, three driver integrated circuits (IC) 84 connected to data electrodes 52 of a PDP 51 with scanning electrodes 53 and common electrodes 54 are provided in an address driver circuit 83. The address driver circuit 83 is further provided with a temperature detection circuit 85. A control circuit 67 inputs a data signal DATA, a clock signal CLOCK, a blank signal BLANK and a latch signal LATCH to the address driver circuit 83. The control circuit 67 is provided with a display data controller 68 and a panel drive controller 69, the display data controller 68 generates the data signal DATA based on the video signal that has been input, and the panel drive controller 69 generates the clock signal CLOCK, the blank signal BLANK and the latch signal LATCH. A control signal from a microcomputer 81 is input to the control circuit 67. Note that a temperature detection result from the temperature detection circuit 85 is input to the microcomputer 81, and the microcomputer 81 also controls an operation of a power source 82 that supplies a power source voltage to the address driver circuit 83 based on the detection result.
According to the foregoing display, the power source voltage can be controlled corresponding to the temperature of the address driver circuit 83.
Note that display where the maximum power loss occurs in the data driver is one-dot stagger display, that is, when one display cell is in a light emission state, all display cells adjacent (above, under, right and left) to the display cell are in a non-emission state, and furthermore, all display cells adjacent (above, under, right and left) to these display cells in the non-emission state are in an emission state, and such relation is formed in entire panel.
However, since detection of the current consumption is performed in one frame unit of the display disclosed in Japanese Patent No. 2853537, no protection is performed unless the current consumption in entire one frame exceeds the reference value even if the sub-field whose current consumption becomes temporarily high is in one frame, for example, even if sub-fields whose current consumption becomes high exist continuously in the latter part of one frame and in the front part of subsequent frame. Therefore, load to the power source may be enormous. Although a driver is provided for each data electrode, the current consumption in one driver may be extremely large because detection of current consumption cannot be made even if the load given to the driver becomes large.
Furthermore, since only temperature detection is performed in the display disclosed in Japanese Patent Laid-Open No. 11-38930, there exists a problem that load to the power source and individual driver cannot be detected directly. For this reason, a temperature as a reference needs to be reduced in order to appropriately reduce the current consumption, and thus causing excessive protection in temperature.